This invention relates to a multiprocessor system intended for fast information processing, and particularly to a multiprocessor system suitable for fast, parallel processing of two-dimensional data such as image data.
Image processing often requires immense computational power which cannot be provided by a single processor, and therefore various image processors of the multiprocessor type have been proposed. Conventional multiprocessor systems, which are simple in structure, have aimed to implement preprocessing such as filtering where ultra high-speed computation is required. In such cases, many processors equal in number to the pixels of an image, each processor merely having a 1-bit processing ability, are operated in parallel to achieve the speed-up of the overall process (called "complete parallel processing type"), as presented under the title of "An LSI Adaptive Array Processor" in the 1982 Annual conference of International Solid State Circuits. The preprocessing by the multiple processors is followed by the main processing including image feature extraction and structural analysis, which have been commited to programs of a general-purpose microcomputer (having high-level arithmetic/logic instructions) at the sacrifice of the processing speed, or handed over to custom-designed hardware devices oriented to specific system purposes.
However, as the application field of image processors expands, the required process becomes more sophisticated. Speed-up of only preprocessing no longer makes sense, and a processor which covers more comprehensive processes is now desired. The prior U.S. patent application Ser. No. 687,159 filed by the same applicant (corresponding to JP-A-60-140456 laid open on July 25, 1985) has proposed a data processing system capable of fast and comprehensive processing through the ring-like connection of several processors with high level functions.
When a multiprocessor system is intended to enhance the computational ability, the inter-processor communication and inter-processor data exchange increase the system overhead, resulting in a lower ability than expected. In addition to this general problem, image processing necessitates fast data transfer between adjacent processors in a two-dimensional arrangement. For example, the above-mentioned multiprocessor system of complete parallel processing type has all processors connected such that each one may effect data transfer with processors adjoining in the eight directions. On this account, the circuit scale is large, and because of the limited processor function of 1-bit arithmetic/logic operation and 1-bit data transfer at once, the system oriented to fast preprocessing is not suited for high-level image processing.
The above-mentioned multi-processor system coupled by a ring bus of the preceding patent application was intended to preclude the circuit complexity, but because of its embodying control system, in which the controller checks the status of the ring bus and processors each time before issuing commands sequentially to the processors and ring bus controller in order to ensure a synchronism between data flowing on the ring bus and the processor operation, the system could not provide a satisfactory high-speed performance.
The above control system needs the following six steps of operation in transferring image data from processor 1 to processor N.
Step 1: The controller issues a control command to processor 1 to fetch data from the memory. PA0 Step 2: Processor 1 notifies the controller that it has fetched data from the memory. PA0 Step 3: The controller issues a control command to the ring bus controller to shift the bus data n times. PA0 Step 4: The ring bus controller notifies the controller that it has shifted the data n times. PA0 Step 5: The controller issues a control command to processor N to store the transferred data in its memory. PA0 Step 6: Processor N notifies the controller that it has stored the data in its memory.
These information transactions between the controller and the processors and ring bus controller have been a significant system overhead of the prior control system.